Zipplet's Stuff

Read / write decoder
--------------------

The read/write decoder is composed of a quad input OR gate (7432). The gates
are connected like this:

--------------------------------------------
| Gate | Input A | Input B | Output        |
--------------------------------------------
| 1    | /MREQ   | /RD     | /MEMRD        |
| 2    | /MREQ   | /WR     | /MEMWR        |
| 3    | /IOREQ  | /RD     | /IORD         |
| 4    | /IOREQ  | /WR     | /IOWR         |
--------------------------------------------

These outputs can directly drive the RD/WR lines of other ICs, especially ones
that are 'fussy' such as the 8255A.

Memory bus address decoder
--------------------------

The memory bus address decoder is comprised of a 3-to-8 decoder (74138).
A13-A15 are connected to the 3 inputs A B and C. 2 of the enable inputs are
tied to always-active and the remaining active low input is tied to /MREQ.

Therefore, the decoder is active whenever a memory bus access is made. One
of the 8 outputs will go low, addressing a specific device. This splits up
the address bus into 8*8KB pages.

The first 2 pages are tied to the BIOS NVRAM and 8KB SRAM respectively.
The next 2 page signals are connected to the expansion bus for use by
a future expansion card that needs to map memory into the memory map for
example a video card with display memory.

Currently, the last 4 page signals will be left unused as the bank selectable
large sideways RAM will simply use A15 instead.

IO bus address decoder
----------------------

The Z80's I/O bus is multiplexed with the main memory bus but it makes use
of only the first 8 address lines A0-A7 so we need a second 3-to-8 decoder.
This time A5-A7 are tied to A B and C.

The first enable pin is connected to the 8255A.
The second enable pin will be tied to the Z80 CTC.

Sideways (pageable) RAM
-----------------------

To be written.